mcarswell

yeah, when i only have the processor definitions speedstep works but sleep doesn't work right. with the Method CST block in there sleep works, but i get ACPI_SMC_PlatformPlugin errors and only 2 speeds, 16 and 38.

Yeah, i would rather have them generated automatically. i'm working toward that now. got rid of SSDT.aml and put GenerateCStates and GeneratePStates back into org.chameleon.boot.plist. what i'm trying to figure out now is why sleep stops working when i remove the Method CST section from Scope _PR in my DSDT, and how to put it back in without causing ACPI_SMC_PlatformPlugin errors.

i'm pretty sure i had done that, but i did it again just in case. i figured out why my sleep stopped working. deleting the method _CST from my DSDT made the errors go away, but broke sleep. any suggestions how i should modify it? Method (CST, 0, NotSerialized) { If (LNotEqual (And (PDCV, 0x0200), 0x0200)) { If (LEqual (NCST, 0x02)) { Store (One, NCST) } } If (LEqual (NCST, Zero)) { Return (C1ST) } If (LEqual (NCST, One)) { Return (CIST) } If (LEqual (NCST, 0x02)) { Return (CMST) } Return (C1ST) }

Thanks again for the reply. Can you tell me if this is right? This is the scope _PR from my DSDT: Scope (_PR) { Processor (CPU0, 0x01, 0x00000410, 0x06) {} Processor (CPU1, 0x02, 0x00000410, 0x06) {} Processor (CPU2, 0x03, 0x00000410, 0x06) {} Processor (CPU3, 0x04, 0x00000410, 0x06) {} Processor (CPU4, 0x05, 0x00000410, 0x06) {} Processor (CPU5, 0x06, 0x00000410, 0x06) {} Processor (CPU6, 0x07, 0x00000410, 0x06) {} Processor (CPU7, 0x08, 0x00000410, 0x06) {} } If I use DSDTSE and extract the SSDT, i get this: /* * Intel ACPI Component Architecture * AML Disassembler version 20091214 * * Disassembly of ./SSDT.aml, Mon Mar 5 15:20:02 2012 * * * Original Table Header: * Signature "SSDT" * Length 0x000001D6 (470) * Revision 0x01 * Checksum 0x10 * OEM ID "AMICPU" * OEM Table ID "PROC" * OEM Revision 0x00000001 (1) * Compiler ID "MSFT" * Compiler Version 0x03000001 (50331649) */ DefinitionBlock ("./SSDT.aml", "SSDT", 1, "AMICPU", "PROC", 0x00000001) { External (\_PR_.OSC_, IntObj) External (\_PR_.PDC_, MethodObj) // 1 Arguments Scope (\_PR) { Processor (P000, 0x01, 0x00000410, 0x06) { Method (_PDC, 1, NotSerialized) { \_PR.PDC (Arg0) } Method (_OSC, 4, NotSerialized) { Return (\_PR.OSC) Arg0 Arg1 Arg2 Arg3 } } Processor (P001, 0x02, 0x00000410, 0x06) { Method (_PDC, 1, NotSerialized) { \_PR.PDC (Arg0) } Method (_OSC, 4, NotSerialized) { Return (\_PR.OSC) Arg0 Arg1 Arg2 Arg3 } } Processor (P002, 0x03, 0x00000410, 0x06) { Method (_PDC, 1, NotSerialized) { \_PR.PDC (Arg0) } Method (_OSC, 4, NotSerialized) { Return (\_PR.OSC) Arg0 Arg1 Arg2 Arg3 } } Processor (P003, 0x04, 0x00000410, 0x06) { Method (_PDC, 1, NotSerialized) { \_PR.PDC (Arg0) } Method (_OSC, 4, NotSerialized) { Return (\_PR.OSC) Arg0 Arg1 Arg2 Arg3 } } Processor (P004, 0x05, 0x00000410, 0x06) { Method (_PDC, 1, NotSerialized) { \_PR.PDC (Arg0) } Method (_OSC, 4, NotSerialized) { Return (\_PR.OSC) Arg0 Arg1 Arg2 Arg3 } } Processor (P005, 0x06, 0x00000410, 0x06) { Method (_PDC, 1, NotSerialized) { \_PR.PDC (Arg0) } Method (_OSC, 4, NotSerialized) { Return (\_PR.OSC) Arg0 Arg1 Arg2 Arg3 } } Processor (P006, 0x07, 0x00000410, 0x06) { Method (_PDC, 1, NotSerialized) { \_PR.PDC (Arg0) } Method (_OSC, 4, NotSerialized) { Return (\_PR.OSC) Arg0 Arg1 Arg2 Arg3 } } Processor (P007, 0x08, 0x00000410, 0x06) { Method (_PDC, 1, NotSerialized) { \_PR.PDC (Arg0) } Method (_OSC, 4, NotSerialized) { Return (\_PR.OSC) Arg0 Arg1 Arg2 Arg3 } } } } The SSDT that i'm actually using is this: /* * Intel ACPI Component Architecture * AML Disassembler version 20110316-64 [Mar 16 2011] * Copyright (c) 2000 - 2011 Intel Corporation * * Disassembly of ssdt_pr.aml, Mon Mar 28 06:05:00 2011 * * Original Table Header: * Signature "SSDT" * Length 0x00000156 (342) * Revision 0x01 * Checksum 0x67 * OEM ID "APPLE " * OEM Table ID "CpuPm" * OEM Revision 0x00001000 (1) * Compiler ID "INTL" * Compiler Version 0x20110316 (537985814) */ DefinitionBlock ("ssdt_pr.aml", "SSDT", 1, "APPLE ", "CpuPm", 0x00001000) { External (\_PR.CPU0, DeviceObj) External (\_PR.CPU1, DeviceObj) External (\_PR.CPU2, DeviceObj) External (\_PR.CPU3, DeviceObj) External (\_PR.CPU4, DeviceObj) External (\_PR.CPU5, DeviceObj) External (\_PR.CPU6, DeviceObj) External (\_PR.CPU7, DeviceObj) Scope (_PR) { Scope (\_PR.CPU0) { Name (_PSS, Package (0x10) // Not required anymore (because APSS is used instead)? { Package (0x06) { 3401, 0x00017318, 0x000A, 0x000A, 0x2600, 0x2600 }, Package (0x06) { 3400, 0x00017318, 0x000A, 0x000A, 0x2200, 0x2200 }, Package (0x06) { 3300, 0x00016B6F, 0x000A, 0x000A, 0x2100, 0x2100 }, Package (0x06) { 3200, 0x000163C6, 0x000A, 0x000A, 0x2000, 0x2000 }, Package (0x06) { 3100, 0x000154BA, 0x000A, 0x000A, 0x1F00, 0x1F00 }, Package (0x06) { 3000, 0x000145F5, 0x000A, 0x000A, 0x1E00, 0x1E00 }, Package (0x06) { 2900, 0x00013776, 0x000A, 0x000A, 0x1D00, 0x1D00 }, Package (0x06) { 2800, 0x0001293C, 0x000A, 0x000A, 0x1C00, 0x1C00 }, Package (0x06) { 2700, 0x00011B47, 0x000A, 0x000A, 0x1B00, 0x1B00 }, Package (0x06) { 2600, 0x00010D96, 0x000A, 0x000A, 0x1A00, 0x1A00 }, Package (0x06) { 2500, 0x00010028, 0x000A, 0x000A, 0x1900, 0x1900 }, Package (0x06) { 2400, 0x0000F2FE, 0x000A, 0x000A, 0x1800, 0x1800 }, Package (0x06) { 2300, 0x0000E616, 0x000A, 0x000A, 0x1700, 0x1700 }, Package (0x06) { 2200, 0x0000D971, 0x000A, 0x000A, 0x1600, 0x1600 }, Package (0x06) { 2100, 0x0000CD0C, 0x000A, 0x000A, 0x1500, 0x1500 }, Package (0x06) { 1600, 0x000092D9, 0x000A, 0x000A, 0x1000, 0x1000 } }) Name (APSN, 0x04) // Number of turbo states (see Intel Datasheet for your CPU). Name (APSS, Package (0x14) // This is the PerformanceStateArray data { Package (0x06) { 3800, 0x00017318, 0x000A, 0x000A, 0x2600, 0x2600 }, // Fourth Turbo State. Package (0x06) { 3700, 0x00017318, 0x000A, 0x000A, 0x2500, 0x2500 }, // Third Turbo State. Package (0x06) { 3600, 0x00017318, 0x000A, 0x000A, 0x2400, 0x2400 }, // Second Turbo State. Package (0x06) { 3500, 0x00017318, 0x000A, 0x000A, 0x2300, 0x2300 }, // First Turbo State. Package (0x06) { 3400, 0x00017318, 0x000A, 0x000A, 0x2200, 0x2200 }, // Maximum non-turbo frequency. Package (0x06) { 3300, 0x00016B6F, 0x000A, 0x000A, 0x2100, 0x2100 }, Package (0x06) { 3200, 0x000163C6, 0x000A, 0x000A, 0x2000, 0x2000 }, Package (0x06) { 3100, 0x000154BA, 0x000A, 0x000A, 0x1F00, 0x1F00 }, Package (0x06) { 3000, 0x000145F5, 0x000A, 0x000A, 0x1E00, 0x1E00 }, Package (0x06) { 2900, 0x00013776, 0x000A, 0x000A, 0x1D00, 0x1D00 }, Package (0x06) { 2800, 0x0001293C, 0x000A, 0x000A, 0x1C00, 0x1C00 }, Package (0x06) { 2700, 0x00011B47, 0x000A, 0x000A, 0x1B00, 0x1B00 }, Package (0x06) { 2600, 0x00010D96, 0x000A, 0x000A, 0x1A00, 0x1A00 }, Package (0x06) { 2500, 0x00010028, 0x000A, 0x000A, 0x1900, 0x1900 }, Package (0x06) { 2400, 0x0000F2FE, 0x000A, 0x000A, 0x1800, 0x1800 }, Package (0x06) { 2300, 0x0000E616, 0x000A, 0x000A, 0x1700, 0x1700 }, Package (0x06) { 2200, 0x0000D971, 0x000A, 0x000A, 0x1600, 0x1600 }, Package (0x06) { 2100, 0x0000CD0C, 0x000A, 0x000A, 0x1500, 0x1500 }, Package (0x06) { 2000, 0x0000C0E9, 0x000A, 0x000A, 0x1400, 0x1400 }, Package (0x06) { 1600, 0x000092D9, 0x000A, 0x000A, 0x1000, 0x1000 } // Lowest Clock frequency. }) Method (ACST, 0, NotSerialized) { Return (Package (0x06) { One, 0x04, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address 0x01, // Access Size ) }, One, 0x03, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000010, // Address 0x03, // Access Size ) }, 0x03, 0xCD, 0x01F4 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000020, // Address 0x03, // Access Size ) }, 0x06, 0xF5, 0x015E }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000030, // Address 0x03, // Access Size ) }, 0x07, 0xF5, 0xC8 } }) } Name (_PPC, Zero) Name (_PCT, Package (0x02) { ResourceTemplate () { Register (FFixedHW, 0x40, // Bit Width 0x00, // Bit Offset 0x0000000000000199, // Address ,) }, ResourceTemplate () { Register (FFixedHW, 0x10, // Bit Width 0x00, // Bit Offset 0x0000000000000198, // Address ,) } }) Name (_PTC, Package (0x02) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) } }) Name (_PSD, Package (0x05) { 0x05, Zero, Zero, 0xFC, 0x08 }) Method (_CST, 0, NotSerialized) { Return (Package (0x04) { 0x03, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, One, One, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000414, // Address ,) }, 0x02, 0x50, 0x01F4 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000415, // Address ,) }, 0x03, 0x68, 0x015E } }) } Name (_TPC, Zero) Name (_TSS, Package (0x08) { Package (0x05) { 0x64, 0x03E8, Zero, Zero, Zero }, Package (0x05) { 0x58, 0x036B, Zero, 0x1E, Zero }, Package (0x05) { 0x4B, 0x02EE, Zero, 0x1C, Zero }, Package (0x05) { 0x3F, 0x0271, Zero, 0x1A, Zero }, Package (0x05) { 0x32, 0x01F4, Zero, 0x18, Zero }, Package (0x05) { 0x26, 0x0177, Zero, 0x16, Zero }, Package (0x05) { 0x19, 0xFA, Zero, 0x14, Zero }, Package (0x05) { 0x0D, 0x7D, Zero, 0x12, Zero } }) } Scope (\_PR.CPU1) { Method (APSS, 0, NotSerialized) { Return (\_PR.CPU0.APSS) } Method (_CST, 0, NotSerialized) { Return (\_PR.CPU0._CST) } Method (_PCT, 0, NotSerialized) { Return (\_PR.CPU0._PCT) } Method (_PPC, 0, NotSerialized) { Return (\_PR.CPU0._PPC) } Method (_PTC, 0, NotSerialized) { Return (\_PR.CPU0._PTC) } Method (_PSD, 0, NotSerialized) { Return (\_PR.CPU0._PSD) } Method (_PSS, 0, NotSerialized) { Return (\_PR.CPU0.APSS) } Method (_TPC, 0, NotSerialized) { Return (\_PR.CPU0._TPC) } Method (_TSS, 0, NotSerialized) { Return (\_PR.CPU0._TSS) } } Scope (\_PR.CPU2) { Method (APSS, 0, NotSerialized) { Return (\_PR.CPU0.APSS) } Method (_CST, 0, NotSerialized) { Return (\_PR.CPU0._CST) } Method (_PCT, 0, NotSerialized) { Return (\_PR.CPU0._PCT) } Method (_PPC, 0, NotSerialized) { Return (\_PR.CPU0._PPC) } Method (_PTC, 0, NotSerialized) { Return (\_PR.CPU0._PTC) } Method (_PSD, 0, NotSerialized) { Return (\_PR.CPU0._PSD) } Method (_PSS, 0, NotSerialized) { Return (\_PR.CPU0._PSS) } Method (_TPC, 0, NotSerialized) { Return (\_PR.CPU0._TPC) } Method (_TSS, 0, NotSerialized) { Return (\_PR.CPU0._TSS) } } Scope (\_PR.CPU3) { Method (APSS, 0, NotSerialized) { Return (\_PR.CPU0.APSS) } Method (_CST, 0, NotSerialized) { Return (\_PR.CPU0._CST) } Method (_PCT, 0, NotSerialized) { Return (\_PR.CPU0._PCT) } Method (_PPC, 0, NotSerialized) { Return (\_PR.CPU0._PPC) } Method (_PTC, 0, NotSerialized) { Return (\_PR.CPU0._PTC) } Method (_PSD, 0, NotSerialized) { Return (\_PR.CPU0._PSD) } Method (_PSS, 0, NotSerialized) { Return (\_PR.CPU0._PSS) } Method (_TPC, 0, NotSerialized) { Return (\_PR.CPU0._TPC) } Method (_TSS, 0, NotSerialized) { Return (\_PR.CPU0._TSS) } } Scope (\_PR.CPU4) { Method (APSS, 0, NotSerialized) { Return (\_PR.CPU0.APSS) } Method (_CST, 0, NotSerialized) { Return (\_PR.CPU0._CST) } Method (_PCT, 0, NotSerialized) { Return (\_PR.CPU0._PCT) } Method (_PPC, 0, NotSerialized) { Return (\_PR.CPU0._PPC) } Method (_PTC, 0, NotSerialized) { Return (\_PR.CPU0._PTC) } Method (_PSD, 0, NotSerialized) { Return (\_PR.CPU0._PSD) } Method (_PSS, 0, NotSerialized) { Return (\_PR.CPU0._PSS) } Method (_TPC, 0, NotSerialized) { Return (\_PR.CPU0._TPC) } Method (_TSS, 0, NotSerialized) { Return (\_PR.CPU0._TSS) } } Scope (\_PR.CPU5) { Method (APSS, 0, NotSerialized) { Return (\_PR.CPU0.APSS) } Method (_CST, 0, NotSerialized) { Return (\_PR.CPU0._CST) } Method (_PCT, 0, NotSerialized) { Return (\_PR.CPU0._PCT) } Method (_PPC, 0, NotSerialized) { Return (\_PR.CPU0._PPC) } Method (_PTC, 0, NotSerialized) { Return (\_PR.CPU0._PTC) } Method (_PSD, 0, NotSerialized) { Return (\_PR.CPU0._PSD) } Method (_PSS, 0, NotSerialized) { Return (\_PR.CPU0._PSS) } Method (_TPC, 0, NotSerialized) { Return (\_PR.CPU0._TPC) } Method (_TSS, 0, NotSerialized) { Return (\_PR.CPU0._TSS) } } Scope (\_PR.CPU6) { Method (APSS, 0, NotSerialized) { Return (\_PR.CPU0.APSS) } Method (_CST, 0, NotSerialized) { Return (\_PR.CPU0._CST) } Method (_PCT, 0, NotSerialized) { Return (\_PR.CPU0._PCT) } Method (_PPC, 0, NotSerialized) { Return (\_PR.CPU0._PPC) } Method (_PTC, 0, NotSerialized) { Return (\_PR.CPU0._PTC) } Method (_PSD, 0, NotSerialized) { Return (\_PR.CPU0._PSD) } Method (_PSS, 0, NotSerialized) { Return (\_PR.CPU0._PSS) } Method (_TPC, 0, NotSerialized) { Return (\_PR.CPU0._TPC) } Method (_TSS, 0, NotSerialized) { Return (\_PR.CPU0._TSS) } } Scope (\_PR.CPU7) { Method (APSS, 0, NotSerialized) { Return (\_PR.CPU0.APSS) } Method (_CST, 0, NotSerialized) { Return (\_PR.CPU0._CST) } Method (_PCT, 0, NotSerialized) { Return (\_PR.CPU0._PCT) } Method (_PPC, 0, NotSerialized) { Return (\_PR.CPU0._PPC) } Method (_PTC, 0, NotSerialized) { Return (\_PR.CPU0._PTC) } Method (_PSD, 0, NotSerialized) { Return (\_PR.CPU0._PSD) } Method (_PSS, 0, NotSerialized) { Return (\_PR.CPU0._PSS) } Method (_TPC, 0, NotSerialized) { Return (\_PR.CPU0._TPC) } Method (_TSS, 0, NotSerialized) { Return (\_PR.CPU0._TSS) } } } } also i just noticed that something i did while working on this has caused sleep to no longer work right. when i sleep the computer, the screen goes black but the fans stay on, and it won't wake back up. ...frustrating

i got the processor definitions and my SSDT from this thread: http://www.insanelymac.com/forum/index.php?showtopic=253642 i assumed they would be the same as mine since they're for an i7 2600k also. I compared them to the SSDT i extracted from my system and they look the same. I removed everything from the scope _PR section of my DSDT except the processor definitions and got rid of the ACPI_SMC_PlatformPlugin errors, but i still have this error. ACPI_SMC_CtrlLoop::loadStepperContext - pmCPUControl (pmioctlPStateContext_t) failed, result = 0x16 I removed the GenerateXStates options from my boot.plist and put the SSDT back in /Extra and have 5 working Pstates now: 16 35 36 37 and 38. Maybe this is the best i can hope for?

thanks for the reply. i added the processor definitions to my DSDT and that worked, but caused a kernel panic because of mismatched P states in the SSDT. i deleted the SSDT and booted ok with this: Read HFS+ file: [hd(0,2)/Extra/DSDT.aml] 35744 bytes. ACPI table not found: SSDT.aml FADT: Restart Fix applied! FADT: Using custom DSDT! Found ACPI CPU: CPU0 Found ACPI CPU: CPU1 Found ACPI CPU: CPU2 Found ACPI CPU: CPU3 Found ACPI CPU: CPU4 Found ACPI CPU: CPU5 Found ACPI CPU: CPU6 Found ACPI CPU: CPU7 SSDT with CPU C-States generated successfully P-States: min 0x10, max 0x0 RSDT: Added 1 SSDT table(s) FADT: Restart Fix applied! FADT: Using custom DSDT! P-States: min 0x10, max 0x0 Added 1 SSDT table(s) into XSDT but i'm still only getting 2 states, and these error messages in the kernel log: ACPI_SMC_CtrlLoop::loadStepperContext - pmCPUControl (pmioctlPStateContext_t) failed, result = 0x16 ACPI_SMC_PlatformPlugin::pushCPU_CSTData - _CST evaluation failed ACPI_SMC_PlatformPlugin::registerLPCDriver - WARNING - LPC device initialization failed: C-state power management not initialized

Hi all, If anyone can help me with this problem it would be greatly appreciated. I'm running 10.7.3 on an Asus P8P67 Evo board with an i7 2600k cpu. everything is working great except i can't get C/P states to work. my bootloader is chimera 1.8 and i have a custom DSDT and SSDT, and patched AICPUPM.kext. My LPC device ID is already in AppleLPC.kext and AppleLPC is loading (checked with kextstat). I get this in the kernel.log: ACPI_SMC_PlatformPlugin::pushCPU_CSTData - _CST evaluation failed ACPI_SMC_PlatformPlugin::registerLPCDriver - WARNING - LPC device initialization failed: C-state power management not initialized and this in bdmesg Read HFS+ file: [hd(0,2)/Extra/DSDT.aml] 35744 bytes. Read HFS+ file: [hd(0,2)/Extra/SSDT.aml] 2829 bytes. ACPI table not found: SSDT-1.aml FADT: Restart Fix applied! FADT: Using custom DSDT! ACPI CPUs not found: C-States not generated !!! ACPI CPUs not found: P-States not generated !!! RSDT: Added 1 SSDT table(s) FADT: Restart Fix applied! FADT: Using custom DSDT! ACPI CPUs not found: C-States not generated !!! ACPI CPUs not found: P-States not generated !!! Added 1 SSDT table(s) into XSDT checking with MSRDumper i get 2 states: 16 and 34 (no turbo, which is set to manual 43 in bios) Any ideas what i should try to at least get turbo working? Thanks!